The invention relates to a method for clamping a semiconductor device in a manufacturing process using a wafer with deposited material layers causing wafer bowing stress, wherein in particular the wafer is at least 200 mm in diameter.
In the technical process of manufacturing semiconductor devices from wafers (e.g. disks on the basis of silicon) it is common and necessary to apply a lithographic process frequently in the process. In the lithographic process the overlay performance depends on the wafer conditions. Overlay errors may derive e.g. from applying hot processes or processes like chemical mechanical polishing (CMP) and have negative influences on the overlay performance. The errors usually occur due to residuals visible on the wafer surface after the performance of process steps. They can be divided into linear and non-linear overlay errors, whereby only linear or systematic overlay errors can be corrected by varying machine parameters of the exposure tools such as a stepper by optimization of the stepper parameters.
Non-linear overlay errors, which usually cannot be corrected automatically by the manufacturing tools, cause high rework rates resulting in general in a loss of yield. As some of these errors are not correctable, even the rework may show no success.
Beside the aforementioned effects causing non-linear overlay errors, a new root cause especially came up with the wafer technology using wafers of at least 200 mm in diameter. In process steps where a front side and a backside of the wafer is deposited with at least one material layer having tensile or compressive stress such as nitride, polysilicon or different types of oxides, mechanical stress causes wafer warpage, e.g. as a result of forming a structure over the front side of the wafer by etching parts of the material layer. It has been observed that the scale of warpage increases with a larger diameter of the wafer. Due to a significant misalignment in the lithographic process after, for example, an element isolation process, non-linear overlay errors may occur.
Other problems in manufacturing may arise with processes that use electrostatic chucks or physical clamping rings for holding the wafer during etch or thin film deposition processes. Warped wafers coming into the processes cause robotic wafer handling failures due to vacuum sealing problems or process faults due to a leakage of backside cooling gases on the electrostatic chuck. In diffusion operations, precise loading of the wafers into the boats that are inserted in the furnace are affected by warped wafers resulting in wafer breakage or chipping, damage to the boat, or dropped wafers. Operations such as wet chemical processing that load wafers into holders by vacuum clamping on the wafer backside are also impacted by warped wafers. In CMP operations, warped wafers cause process non-uniformity errors due to the warpage affecting the polishing of the entire wafer surface. Further processes that can be impacted in their performance by wafer warpage are ion implantation processes, mask making or metrology processes.
In U.S. Pat. No. 5,856,230 there is disclosed a method for making a field oxide, by which wafer warpage is minimized when a local oxidation of silicon process is applied to a large wafer. A material layer having a compressive stress and a nitride are laminated over the backside of the wafer, so that the compressive stress of the material layer complementarily interacts with the tensile stress of the nitride. The method contains the steps of depositing an oxide layer and the material layer over the front side and the backside of the wafer in addition to the standard LOCOS-process steps. The effects herein may be an increase of manufacturing costs and an increase of process time.
It is accordingly an object of the invention to provide a method for clamping a semiconductor device in a manufacturing process which overcomes the above-mentioned disadvantages of the prior art methods of this general type, which reduces or prevents the problems of the aforementioned wafer warpage, the method being applicable to multiple process sequences of semiconductor manufacturing with respect to low costs and process time.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for clamping a semiconductor device in a manufacturing process. The method includes the steps of providing a wafer having a front side and a backside, depositing at least one encapsulating material layer over the front side and the backside of the wafer, and etching the encapsulating material layer selectively over the front side of the wafer to form a predetermined structure, thereby causing wafer warpage as a result of a bowing stress of the encapsulating material layer. The encapsulating material layer is then removed over the backside of the wafer partially or completely from the backside in accordance with a desired reduction of the bowing stress. The semiconductor device is then clamped electrostatically, physically, or by use of a vacuum in a further course of a manufacturing process for holding the wafer.
The provided method is applicable to a multiple processes containing the aforementioned sequences of process steps. The provided method therefore is applicable, for example, in DRAM technologies and in processes for manufacturing logic circuits or micromechanic components. The effect of reducing wafer warpage can be observed significantly at wafers of at least 200 mm in diameter. Especially when using wafers of 300 mm in diameter and larger, the wafer warpage caused by material layers plays a fairly important role for the performance of the aforementioned processes, in comparison to effects caused by processes such as CMP or hot processes, because of the different thickness-to-area-ratio. Furthermore the problem of overlay distortions caused by wafer warpage can be observed especially at backend of-line lithography processes (BEOL).
In lithographic processes, there is a reduced amount of defocus or non-linear overlay errors as a result of reduced wafer warpage. Thus, process improvements can be observed with no or less rework rates and a reduction in yield loss.
Concerning the other aforementioned processes, as a result of reduced wafer warpage there are no or less robotic wafer handling failures or process faults impacted by wafer warpage. Precise loading of the wafers into boats that are inserted in a furnace is improved. In CMP operations, reduced process non-uniformity errors due to wafer warpage can be achieved.
Further it is not necessary to deposit a novel kind of layer interacting with the stress of the encapsulating material layer. This results in low costs and process time. It takes into account that for several reasons it can be disadvantageous to deposit multiple layers over the backside of the wafer. This could take influence on other processes or prevent the wafer surface from having a flat backside that could be necessary with regard to the requirements of the wafer or stepper chuck.
According to the present invention, the material layer or material layers can be removed completely or partially depending on the process and its requirements according to the reduction of the warpage. In case of removing the layers partially, which helps to destress the wafer, the corresponding process time can be shortened. For partial removal, the layer is removed within a circular area from the backside of the wafer by suitable etching techniques. The layer is still present within the area surrounding the inner circular area.
For example, the material layer or material layers can be formed of nitride, polysilicon or all known variations of oxides such as BPSG or siliconoxide. They all have more or less compressive or tensile stress to cause wafer warpage.
Advantageously, in a lithographic process the invention reduces the necessity of non-linear correction algorithms with respect to reduced software and measurement capacity and therefore reduced process cycle times. It eliminates the root cause with the effect that no compensation of the symptoms is necessary. Over all a better product quality can be achieved.
According to an embodiment of the present invention, the deposition and the removal of the material layer on the backside is part of a common DRAM process forming gate contact interconnects over the front side of the wafer. The wafer is a silicon substrate with active areas at that stage. For forming gate contacts the backside layer may be removed partially or completely according to the desired amount of reduction of bowing stress. The accompanying sequence of process steps is described with respect to the drawings below.
In a preferred embodiment, the material layer or material layers are removed by spin etch processing using an acid process. In a spin etch tool preferably a chemical consisting of HF (e.g. 49% HF at 40xc2x0 C.) etches the layers on the backside of the wafer. In the aforementioned DRAM process, the process time could be about 360 seconds to remove as much nitride as necessary to reduce the wafer warpage to acceptable levels. To take it off completely it can take about 720 seconds, for example. Thereby it has to be taken into account that the attack on the wafer edge on the front side of the wafer should be minimized.
In a further embodiment of the invention, the wafer bowing stress of the material layer on the backside is relieved by removing the material layer by a plasma back-etching process in a single wafer tool or batch tool with the front side of the wafer protected by a removable protective material. Preferably, the protective material can be formed of a film such as photoresist or other suitable removable film. Advantageously the process uses plasma processing to remove the backside films using chemistries that are known in the art to achieve rapid throughputs. After the processing, the front side protecting film is removed by a solvent, ashing or other cleaning processes.
According to another embodiment, the material layer is removed by a liquid acid processing in an immersion tank in a single wafer tool or a batch tool with the front side of the wafer protected by a removable protective material. Advantageously, the process uses an acid, acids, or other chemical combinations to remove the backside films using chemistries that are known in the art to achieve rapid throughputs. After the processing, the front side protecting film is removed by solvent, ashing or other cleaning processes.
In a further embodiment, the material layer is removed by a vapor phase processing in a single wafer tool or batch tool. Preferably, the process uses an acid vapor, vapor of various acids or other chemical vapor combinations to remove the backside films using chemistries that are known in the art to achieve rapid throughputs. After the processing, the front side protecting film is removed by solvent, ashing or other cleaning processes. In some tool configurations, the front side of the wafer may be adequately protected such that front side protection is not required. Otherwise the front side of the wafer has to be protected by a removable protective material before starting the process.
According to another embodiment, the material layer is removed by CMP processing with the front side of the wafer protected by a removable protecting material. Advantageously, the process uses a slurry or slurry materials, composed of abrasive materials that chemically facilitate the removal by physical methods, that are known in the art to achieve rapid throughputs. After the processing, the front side protecting film is removed by solvent, ashing, physical peel-back of protecting films or other cleaning processes.
In accordance with another mode of the invention, there is the step of forming the encapsulating material layer from nitride.
In accordance with a further mode of the invention, there are the steps of providing the wafer as a silicon substrate with active areas, depositing a gate oxide layer, a polysilicon layer and a metal layer over the front side of the wafer, and performing the step of the depositing of the encapsulating material layer over the front side and the backside of the wafer. The gate oxide layer, the polysilicon layer, the metal layer, and the encapsulating material layer are then etched selectively over the front side of the wafer to form the predetermined structure functioning as gate contact interconnects. An insulating layer is deposited over the gate contact interconnects on the front side of the wafer. An ion implantation process is applied over the front side of the wafer. The encapsulating material layer is partially etched on the backside of the wafer. At least one insulating layer is deposited over the front side of the wafer. A lithographic process is applied over the front side to form a structured mask for assisting in an etching process to form contacts to implanted areas of the silicon substrate.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for clamping of a semiconductor device in a manufacturing process, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.